Reversible Cipher

ABSTRACT

A cipher device having a number of data bits in an input register corresponding to a data unit element, a sudoku filter coupled with the input register, and a data selector coupled with the sudoku filter and the input register. A fob cipher device has a FPGA programmed to perform encrypting of a plaintext with a transposed Sudoku to form a first ciphertext and encrypting the first ciphertext with pseudorandom mixing bits to form a second ciphertext. A reversible encryption method includes encrypting plaintext with a transposed Sudoku forming a first ciphertext, encrypting the first ciphertext with pseudorandom mixing bits forming a second ciphertext, and outputting the plaintext-corresponding second ciphertext.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to ciphering apparatus and methods and, inparticular, stream-type block cipher apparatus and methods.

2. Background Art

The Internet has become a powerful public communication and informationtool. Even so, secure communication between peer computing nodes(peer-to-peer communication) has become vulnerable to attack by thenefarious and by privacy-loathing governments around the world. Securepeer-to-peer communications on the Internet enhances the networks'utility as a means of commerce. However, a wide-used form ofsecurity—Public Key Encryption, including RSA—is vulnerable tomathematical attacks. Another form, DES is no longer considered toprovide enough security for secure transactions. Yet another, RC4, isexpensive in that it requires a large amount of memory and setup time.Almost all current ciphers require manual human intervention to work; itis highly desirable to have well-distributed random number generators toprovide for secure keys, and humans are notoriously bad at generatinglengthy random numbers and at recalling, long, truly random passwords.Ciphering apparatus and methods avoiding these shortcomings aredesirable.

SUMMARY

The present invention includes methods and apparatus for stream-typeblock ciphering. A method of securing data, includes receiving aplaintext data unit; encrypting a plaintext data unit with a transposedSudoku to form a first ciphertext unit; encrypting the first ciphertextunit with pseudorandom mixing bits to form a second ciphertext unit; andoutputting the second ciphertext unit corresponding to the plaintextdata unit. Another method, for deciphering, includes receiving a thirdciphertext data unit; encrypting the third ciphertext data unit with atransposed Sudoku to form a fourth ciphertext unit; encrypting thefourth ciphertext unit with pseudorandom mixing bits to form a secondplaintext data unit; and outputting the second plaintext data unitcorresponding to the third ciphertext unit.

An apparatus for securing data includes an input register having apredetermined number of data bits corresponding to a data unit element;a sudoku filter coupled with the input register having a predeterminednumber of elements corresponding to the predetermined number of databits; and a data selector coupled with the sudoku filter and the inputregister. Another apparatus, in a fob configuration, includes: an inputport, a FPGA coupled with the input port, and configured using an HDL toperform encrypting a plaintext data unit with a transposed Sudoku toform a first ciphertext unit and encrypting the first ciphertext unitwith pseudorandom mixing bits to form a second ciphertext unit; and anoutput port coupled with the FPGA. The FPGA, the input port, and theoutput port are configured as a FOB device; and the plaintext isreceived at an input port and a corresponding second ciphertext unit istransmitted to the output port. In certain embodiments, a memory devicecoupled with the FPGA. In others, the input and output ports are USBports.

BRIEF DESCRIPTION OF DRAWINGS

The invention is generally shown by way of reference to the accompanyingdrawings in which:

FIG. 1 is a logic block diagram of a cipher device, in accordance withthe teachings of the invention herein;

FIG. 2 is a logic flow diagram of a first program algorithm used inaccordance with the teachings of the invention herein;

FIG. 3 is an example JAVA® programming code representation of the firstprogram algorithm, in accordance with the teachings of the inventionherein;

FIG. 4 is a logic flow diagram of a second program algorithm used withthe first program algorithm, in accordance with the teachings of theinvention herein in accordance with the teachings of the inventionherein;

FIG. 5 is an example JAVA® programming code representation of the secondprogram algorithm, in accordance with the teachings of the inventionherein;

FIG. 6 is a logic flow diagram of a third program algorithm used withthe first program algorithm, in accordance with the teachings of theinvention herein in accordance with the teachings of the inventionherein; and

FIG. 7 is an example JAVA® programming code representation of the thirdprogram algorithm, in accordance with the teachings of the inventionherein; and

FIG. 8 is a block logic diagram of a fob-type cipher device, inaccordance with the teachings of the invention herein.

In the figures, which are not drawn to scale, like numerals refer tolike features throughout the description.

DETAILED DESCRIPTION OF EMBODIMENTS

The cipher method and apparatus herein provide a reversibleelement-oriented (stream-type) block cipher and cipher device that canbe easily implemented in hardware or software. Without limitation, thehardware can include firmware or hardware description languages, and thesoftware can include one or more of compiled, scripting or server-sideprogramming languages. Hardware description languages can includeVerilog® HDL language, SystemVerilog language, VHDL language, andSystemC language. Compiled languages can include platform-independentJAVA® or Python programming language, or conventionally compiled codesuch as C++®, C®, Objective C, FORTRAN, Pascal, or BASIC programminglanguages. Scripting languages also may be used, such as interpretedBASIC language, JavaScript®, AppleScript®, ActionScript® or Lingo®programming languages. A server-side language includes pert, PHP, CGI,ASP or JSP server-side language. It is known to those of ordinary skillin the art that a scripting-type language tends to operate more slowlythan a hardware, a compiled, or a server-side language. Indeed, ahardware language (HDL) usually is “compiled” into a physical electronicdevice, which can realize the reversible cipher herein at wire speed.The physical electronic device can be a cipher device included as alightweight cryptofilter on a playback device that uses the cipherdevice as part of a media content protection or digital rightsmanagement scheme.

This reversible cipher or cipher device can be block-operable on apayload, such as a pixel, a file, or a data stream, although the cipherpossesses some stream-mode characteristics. Mutatis mutandi, thereversible cipher or cipher device can be used on a bit payload, as in astream-based cipher protocol. The reversible cipher or cipher deviceherein may be used in a modem, in a computer, in a computer tablet, in amedium (video, audio, or A/V) replay device, in a television, in a movieprojection apparatus, in a smart phone, in sensitive or proprietary datafiles, in self-extracting archives, in managed digital right files, andin other applications where reversible ciphers or cipher devices may beused. The reversible cipher or cipher device can use selectable mixingvalues in a pseudorandom number generator within the cipher operations.The reversible cipher also can be configured to integrate a password,which may be used to encrypt and decrypt the payload at the source anddestination, respectively, using a predetermined mixing value set.

As typified by FIG. 1, the cipher device 110 in accordance with thepresent embodiments can include an input register or bits list 20, asudoku (filter) 60 coupled to the input register, and at least onemultiplexer (MUX) or data selector 90, from which a cipher value isoutput, coupled to sudoku 60 and input register 20. Working memory 70can be used to store intermediate values, variables, and pointers duringoperations. Device 110 also can include process control unit (PCU) 80 tomanipulate instructions and values in respective elements. PCU 80 may beconstituted of a FPGA, a CPLD, or a programmed microprocessor ormicrocontroller. Similarly, FPGA or CPLD also may include memory,registers, a sudoku memory area, a data selector, and hardware toimplement the encryption routines herein (such as “KRYPTOP” or“CIPHER”). PCU 80 is operably coupled with input register 20, sudoku 60,MUX 90, and working memory 70. Input register 20 can be configured toinclude a 1×n grid or array of numbers from a payload, and sudoku device60 may be configured to contain 1×(n−m) values, where n includes thenumber of inputs to the at least one MUX 90, and m, a subset of n, canbe the number of selector lines. For understanding, (m=2) bits “0” and“1” are shown as being coupled to the MUX, although the m bits may bedrawn from any preselected bits of the input register to operate theselection function of the MUX 90. A payload may include a header orfooter used to on or off ciphering and may include a password or otherencrypted message.

Typically, sudoku is a term used for a logic-based, combinatorialnumber-placement puzzle which term here is suggestive of the filter orfilter list used in the present embodiments. The complementary pairs arechosen so inputs will not be ignored in the data selection stage of thisstream cipher. Sudoku 60 can serve to sift bits from register 20. Sudoku60 can receive 4 bits (16 possibilities) and shuffles or filters these 4bits into 10 preselected bit combinations. There can be at least six (6)bits in register 20 and 10 complementary hexadecimal pairs in sudoku 60,for a total of 20 numbers. Twenty suitable example hexadecimal valuesfor a sudoku 60 list can be, without limitation, the set of {8, 14, 1,8, 13, 2, 4, 1, 6, 7, 2, 4, 9, 11, 13, 6, 7, 14, 9, 11}₁₆. These bitcombinations eliminate the 6-of-16 hexadecimal values which may causeinputs to be ignored or can cause a lockup situation. In this example, mis selected to be 2, leaving 4 bits for each sudoku 60 value. Ingeneral, the sudoku list 60 can contain selected ones of 4 bit numbers,as a 10-of-16 filter list. The 6-bit register 20 can be made to assume aunique value between 1 and 63 (1 and 2⁶−1). Preferably, in a four-bitsudoku 60, six complementary values that may cause “don't care” (ignore)states, may be excluded from the 4 bit (HEX) sudoku (filter) list 60,including 0000 (0H), 0011 (3H), 0101 (5H), 1010 (AH), 1100(CH), and1111(FH). Sudoku 60 has 20 elements and because the prime factorizationof 20 is 5, 2, and 2, the value of the sudoku element can be multipliedby 5 to bring the 6 bits in input register 20 into parity with the 20elements in the sudoku array 60. By shifting right four (4) times, i.e.,dividing by 16, the appropriate power of 2 is achieved. For example, 63times 5 equals 315. Dividing 16 into 315 yields 19.6875; because integermathematics can be used, the final value of 19 may be achieved bydropping the fractional value, or 0.6875. The resulting value of 19 iswithin sudoku 60 range, that is, 0 to 19, of 20 elements.

Turning to FIGS. 2 and 3, a general flow diagram of thepassword-integrating ciphering scheme, for convenience, identified as“CIPHER FILE” is described respectively using a logic flow and the JAVA®programming language for clarity, as may be executing on cipher device110. “CIPHER FILE” is an example operational program which illustratesthe logical flow of the “KRYPTOP” and “CIPHER” sub-operations used toreversibly encipher a plaintext message or to decipher an encryptedciphertext message. Code for one or more of “CIPHER FILE,” “KRYPTOP,”and “CIPHER” operations may be stored in PCU 80 or in memory 70allocated to such use. PCU 80 may contain flash memory and may be flashprogrammable. By executing such stored instructions, for example, asdescribed by flow 200, encryption and decryption may be performed. In apayload, a header or footer may be used to turn on and off ciphering,allowing for simple encryption or decryption of a protected block, file,or data stream.

A typical flow “CIPHER FILE” flow 200 can proceed by initializingparameters (S205), selecting a sudoku list (S210), opening input andoutput files (S215), and reading an input data unit (S220) (e.g., apassword character) for enciphering. If a data unit is not available forenciphering (S225), the method proceeds by closing (S230) input andoutput files and indicating completion (S235). If an input data unit isavailable for enciphering, then the method proceeds by performing (S240)the “KRYPTOP” operation upon the input data unit to create a firstenciphered data unit integrating, for example, a password datum orelement, and by performing (S245) the “CIPHER” pseudorandom operation toapply the pseudorandom mixing values to the first ciphertext data unit,thereby creating a second ciphertext data unit. If either of theencryption routines encounters an error, throwing (S250) and announcing(S255) an appropriate error message is performed. Otherwise, writing(S260) the second ciphertext data unit into an output file precedesreading the next input data unit (S220) for enciphering. FIG. 3 is aJAVA® code counterpart to the logic flow in FIG. 2.

FIGS. 4 and 5 illustrate general flow diagram of thepassword-integrating ciphering scheme, for convenience, identified as“KRYPTOP” is described, respectively, using a logic flow and the JAVA®programming language for clarity as may be executed on cipher device110. “KRYPTOP” can be described as a password integration operation. InFIGS. 4 and 5, it is assumed for the sake of exposition that thepassword (pw) to be used has a length (len) 20 characters (c), and thatthe process of FIGS. 2 and 3 continues until all password charactershave been encrypted (I=>len). Two pointers may be used to make atransposition of numbers in sudoku 60. One pointer may be identified as“sdko,” and another may be identified a “psdko.”

First, values in register 20 are shuffled by sudoku 60 selecting acorresponding constant of 10 different constants from the unique randomconstants from of 1 to 63. Each of the random values can augment thevalues in the input register 20. Finally, the input register 20 is ANDedto fit into 6 bits.

Sudoku 60 may be shuffled by the input register 20. Prime number 7 canbe added to sudoku (60) pointer, pskdo, added to it and is thenmodulated, by 20, to point to a new element in the sudoku 60. Thissuboperation [((psdko=+7)% 20)] can be repeated, as desired. The number7 is used because the number 6, the number of elements in the bitregister 20, is not prime and because the number 6 is evenly divisibleby 2 and 3. Also, the number 20, the number of elements in the sudoku60, is evenly divisible by 2 and 5. It can be seen, then, that a primenumber, such as 7, can be used to avoid repetitive numerical symmetries.

The sudoku (60) accesses the input register 20 as scrambled by thepointers. The output from the filter array (60) is passed to the datainputs of at least one data selector or multiplexer (90). Themultiplexer (90) has its selector inputs provided from the remainingbits from the input register 20 as scrambled by index. The output fromthe multiplexer (90) is the cipher output (100). The output from themultiplexer (90) is the cipher bit (100) to be combined (exclusive or)with the plain text to become the cipher text. The cipher text is thentransmitted. When received at the other end, the cipher text is combined(exclusive or) with an identically generated cipher bit (100) to becomethe plain text once again.

FIGS. 6 and 7 illustrate general flow diagram of thepassword-integrating ciphering scheme, for convenience, identified as“CIPHER” is described, respectively, using a logic flow and the JAVA®programming language for clarity as may be executed on cipher device110. “CIPHER” may be described as a pseudorandom number generatoroperation, which may be used to encipher plaintext or to decipherciphertext. Variables SDKO and PDSKO may be transposed and thenoperation turns over to the cases of a SWITCH statement. Each casestatement embodies one of the 10-of-16 filtering functions of the sudoku60. Each of the bits statement for a corresponding switch case isgenerally associated with a selectable mixing value. The values selectedfor mixing values can be important in that one difference in a mixingvalue can result in a completely different cipher. So, symmetry ofmixing values may be used to produce a reversible cipher—a ciphertextmessage mixed with the same mixing values as those used to encipher thecorresponding plaintext can produce the deciphered plaintext. A changein any of the value, the polarity, the evenness or the position in themixing values may produce a ciphertext that does not match thecorresponding plaintext, and the ciphertext used with different mixingvalues can end up with a nonsensical plaintext output.

In one embodiment shown in FIGS. 6 and 7, positive and negative valuesof numbers between 1 and 31 were selected, drawing an equal number ofpositive and negative numbers around a mode of the numbers. Such sign,symmetry, modality, and selection are for example only and otherembodiments of the present invention are not so restricted, for example,in a general case. It may be possible to have the mixing values assignedin advance of an enciphering or a deciphering transaction, for example,by a content distributor over the Internet to a playback device, whichmay include cipher device 110, although such device is not mandatory topractice the method described herein. In any case, once the mixingvalues are selected, elements of a password, such as a character, may beencrypted into a ciphertext message, which serves, for example, as adecryption key.

In another embodiment, shown in FIG. 8, a cipher device, such as cipherdevice 110 can be implemented in a fob-like cipher device 810 containingan FPGA 820 and flash memory 830. An example embodiment of cipher devicecan be configured to have a first USB port 840 and a second USB port850, and include JTAG header support 860 a, b, to the USB ports 840,850. FPGA 820 can be programmed to execute code, for example, inaccordance with the operations illustrated by FIGS. 2-7.

While the invention has been described in terms of various specificembodiments, those skilled in the art will recognize that the inventioncan be practiced with modification within the spirit and scope of theclaims.

1. A method of securing data, comprising: receiving a plaintext data unit; encrypting a plaintext data unit with a transposed Sudoku to form a first ciphertext unit; encrypting the first ciphertext unit with pseudorandom mixing bits to form a second ciphertext unit; and outputting the second ciphertext unit corresponding to the plaintext data unit.
 2. The method of claim 1 further comprising: receiving a third ciphertext data unit; encrypting the third ciphertext data unit with a transposed Sudoku to form a fourth ciphertext unit; encrypting the fourth ciphertext unit with pseudorandom mixing bits to form a second plaintext data unit; and outputting the second plaintext data unit corresponding to the third ciphertext unit.
 3. A cipher device, comprising: an input register having a predetermined number of data bits corresponding to a data unit element; a sudoku filter coupled with the input register having a predetermined number of elements corresponding to the predetermined number of data bits; and a data selector coupled with the sudoku filter and the input register.
 4. A cipher device, comprising: an input port; a FPGA coupled with the input port, and configured using an HDL to perform encrypting a plaintext data unit with a transposed Sudoku to form a first ciphertext unit and encrypting the first ciphertext unit with pseudorandom mixing bits to form a second ciphertext unit; and an output port coupled with the FPGA; wherein the FPGA, the input port, and the output port are configured as a FOB device, and wherein the plaintext is received at an input port and a corresponding second ciphertext unit is transmitted to the output port.
 5. The cipher device of claim 4, further comprising: a memory device coupled with the FPGA.
 6. The cipher device of claim 4 where the input port is a USB port and the output port is a USB port
 7. A reversible cipher device, comprising: a data input register; a transposed 10 of 16 filter coupled to the data input register; and a 1 of 4 multiplexer having 4 data inputs coupled to the transposed 10 of 16 filter and having 2 selector inputs coupled to the data input register, wherein the cipher device is configured to produce pseudorandom bits using the 1 of 4 multiplexer and combine the pseudorandom bits with a plaintext data unit using an exclusive or function to produce a ciphertext data unit.
 8. The reversible cipher device of claim 7, wherein the ciphertext unit cannot be decrypted without an identically configured cipher device.
 9. The reversible cipher device of claim 7, further comprising: a process control unit (PCU) operably coupled to the data input register, the transposed 10 of 16 filter; and a USB port coupled to the PCU.
 10. The reversible cipher device of claim 9, wherein the PCU and the USB port are configured to receive input and transmit output allowing reconfiguration, enciphering, and deciphering.
 11. The reversible cipher device of claim 10, wherein the PCU, the USB port, the data input register, the transposed 10 of 16 filter, and the 1 of 4 multiplexer are arranged on a field-programmable gate array (FPGA).
 12. The reversible cipher device of claim 10, wherein the PCU, the USB port, the data input register, the transposed 10 of 16 filter, and the 1 of 4 multiplexer are arranged in a fob device.
 13. The reversible cipher device of claim 7, further comprising a field-programmable gate array (FPGA) coupled with the data input register and the transposed 10 of 16 filter and configured using a hardware description language (HDL) to instruct the cipher device to produce the pseudorandom bits and combine the pseudorandom bits with the plaintext data unit using an exclusive or function to produce the ciphertext data unit.
 14. The reversible cipher device of claim 13, wherein the FPGA is arranged in a fob device and is coupled to an input port and an output port, wherein the plaintext is received at the input port and the ciphertext data unit is transmitted to the output port.
 15. The reversible cipher device of claim 14, wherein the input port is a USB port and the output port is a different USB port.
 16. The reversible cipher device of claim 7, further comprising a hardware description language (HDL) configured to instruct the 1 of 4 multiplexer to produce the pseudorandom bits and combine the pseudorandom bits with the plaintext data unit using an exclusive or function to produce the ciphertext data unit.
 17. The reversible cipher device of claim 7, further configured with a stream-based cipher protocol allowing the 1 of 4 multiplexer to combine the pseudorandom bits with a data stream to produce a ciphertext data stream.
 18. The reversible cipher device of claim 7, further configured to integrate a password into the ciphertext data unit, which may be used to encrypt and decrypt the plaintext data unit at a source and a destination.
 19. The reversible cipher device of claim 7, wherein the 10 of 16 filter is configured to shuffle or filter data received from the 4 data inputs into 10 preselected bit combinations.
 20. A cipher device, comprising: a data input register; a filter coupled to the data input register and configured to shuffle or filter bits received from the data input register into preselected bit combinations, wherein the filter is configured to exclude values that may cause ignore states; and a multiplexer having data inputs coupled to the filter and having selector inputs coupled to the data input register, wherein the cipher device is configured to produce pseudorandom bits using the multiplexer and combine the pseudorandom bits with a plaintext data unit using an exclusive or function to produce a ciphertext data unit.
 21. The cipher device of claim 20, further comprising: a process control unit (PCU) operably coupled to the data input register, the filter, and the multiplexer; and a USB port coupled to the PCU.
 22. The cipher device of claim 21, wherein the filter is a 10 of 16 filter and the multiplexer is a 1 of 4 multiplexer having 4 data inputs coupled to the transposed 10 of 16 filter and having 2 selector inputs coupled to the data input register.
 23. The cipher device of claim 22, wherein the PCU, the USB port, the data input register, the transposed 10 of 16 filter, and the 1 of 4 multiplexer are arranged on a field-programmable gate array (FPGA) in a fob device.
 24. The cipher device of claim 20, further comprising a field-programmable gate array (FPGA) coupled with the multiplexer and configured using a hardware description language (HDL) to use the multiplexer to produce the pseudorandom bits and combine the pseudorandom bits with the plaintext data unit using an exclusive or function to produce the ciphertext data unit. 